Protruding contact for integrated chip

ABSTRACT

The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.

REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 13/706,615 filed on Dec. 6, 2012.

BACKGROUND

Modern day integrated chips contain millions of semiconductor devices. The semiconductor devices are electrically interconnected by way of back-end-of-the-line metal interconnect layers that are formed above the devices on an integrated chip. A typical integrated chip comprises a plurality of back-end-of-the-line metal interconnect layers embedded within dielectric material. The metal interconnect layers contain vertically alternating layers of metal wires coupled together with metal contacts (i.e., vias). The size of the metal interconnect layers increases from thin metal lines that connect to the devices, to thick metal lines that connect to off chip components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B illustrate cross-sectional views of a conventional back-end-of-the-line metallization process.

FIG. 2 is a flow diagram of some embodiments of a method for forming a back-end-of-the-line metal contact.

FIG. 3 is a cross-sectional view of an integrated chip having a disclosed back-end-of-the-line metal interconnect stack.

FIG. 4 is a flow diagram of some embodiments of a method for forming a back-end-of-the-line metal contact.

FIGS. 5-7 and FIGS. 9-15 are cross-sectional views of some embodiments of an example semiconductor substrate upon which a method of forming a back-end-of-the-line metal contact is performed.

FIGS. 8A-8G illustrate some examples of sacrificial UTDL compounds.

DETAILED DESCRIPTION

The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It will be appreciated that the details of the figures are not intended to limit the disclosure, but rather are non-limiting embodiments. For example, it may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding.

FIGS. 1A-1B are cross-sectional views, 100 and 114, of an integrated chip illustrating a conventional back-end-of-the-line metallization process. As shown in cross-sectional view 100, the metallization process comprises depositing an etch stop layer 104 on an underlying substrate 102, and then subsequently forming an inter-level dielectric (ILD) layer 106 on the etch stop layer 104. A masking layer 108 is formed on the ILD layer 106 and the ILD layer 106 is selectively etched to form a via hole. A barrier layer 110 is then deposited onto the substrate and metal 112 is deposited to fill the via hole.

After metal 112 has been deposited, a chemical mechanical polishing (CMP) process is performed to planarize the substrate, as shown in cross-sectional view 114. Planarization of the substrate removes excess material from a top surface of the substrate along line 116, resulting in a substantially flat surface upon which a subsequent metal layer is formed. However, low pattern density of metal 112 induces a faster metal etching rate that causes the metal 112 to recess or “dish”, forming a metal contact 118 that is recessed below a top surface 106 a of the ILD layer 106 by a depth d.

As the size of metal contacts gets smaller (e.g., ≦14 nm), the via hole gets smaller, and the recess formed by “dishing” becomes more difficult to fill. Failure to properly fill the recess results in an RC open between the metal contact 118 and an overlying metal wire. While etching (e.g., wet etching or dry plasma) can be used to remove the ILD layer 106 that is above metal contact 118 after the CMP process is performed, such etching may damage the metal contact 118 and the ILD layer 106.

Accordingly, the present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer. By forming a metal contact that protrudes from the ILD layer, RC opens due to CMP “dishing” are eliminated

FIG. 2 is a flow diagram of some embodiments of a method 200 for forming a back-end-of-the-line metal contact. Although method 200 is described in regards to a back-end-of-the-line integration scheme in which the metal contact is formed within a via hole located in an inter-level dielectric layer, it will be appreciated that the method may also apply to a back-end-of-the line integration scheme in which the metal contact is formed prior to deposition of a surrounding inter-level dielectric material.

At act 202, a sacrificial UV/thermal decomposition layer (UTDL) is deposited above an inter-level dielectric (ILD) layer. The sacrificial UTDL comprises a material that decomposes when exposed to thermal energy (e.g., a raised temperature) or ultra-violet radiation. In some embodiments, the sacrificial UTDL comprises a low molecular weight oligomer (e.g., a polymer having a small number of monomers).

At act 204, a metal contact is formed that extends through the ILD layer and the sacrificial UTDL. The metal contact provides for an electrical connection between an underlying conductive layer (e.g., an underlying metal layer, semiconductor device) and a top surface of the ILD layer. In some embodiments, the metal contact is formed by selectively etching the ILD layer and the sacrificial UTDL to form a via hole, which is subsequently filled with a metal.

At act 206, a chemical mechanical polishing (CMP) process, which stops on the sacrificial UTDL, is performed to form a planar surface comprising the sacrificial UTDL. The CMP process utilizes a combination of chemical and mechanical forces to remove material from a surface of a substrate.

At act 208, an ultra-violet (UV) exposure or a thermal anneal is performed. The UV exposure or thermal anneal decomposes the sacrificial UTDL so that the sacrificial UTDL is removed from the surface of the substrate, leaving the underlying ILD layer exposed. The UV exposure or thermal anneal removes the sacrificial UTDL without other processing steps (e.g., a rinsing step).

By removing the sacrificial UTDL, the top surface of the metal contact is raised relative to the surrounding ILD layer so that the metal contact forms a protrusion from the ILD layer having a positive relief. Furthermore, the use of a UV exposure or thermal anneal achieves the protrusion without affecting (i.e., damaging) the underlying ILD layer or the metal contact. By removing the sacrificial UTDL any “dishing” (i.e., negative relief) of the metal contact is eliminated and replaced by a metal contact that protrudes from a top surface of the ILD layer.

At 210, a metal wire is formed above the metal contact. Forming the metal wire above the metal contact causes the positive relief of the metal contact to be embedded within the metal wire (i.e., surrounded by the metal wire on three adjacent sides), thereby eliminating RC opens due to CMP “dishing”.

FIG. 3 is a cross-sectional view of an integrated chip 300 having a disclosed back-end-of-the-line metal interconnect stack.

The integrated chip 300 comprises an inter-level dielectric (ILD) layer 306 disposed above an underlying substrate 102. In various embodiments, the substrate 102 may comprise one or more devices and/or one or more metal interconnect layers 302 (e.g., metal wire layers and/or metal contact layers). The ILD layer 306 may comprise a low-k material or an ultra low-k dielectric material, having a dielectric constant (κ) that is less than 3.9. An etch stop layer 104 is disposed between the substrate 102 and the ILD layer 306. In some embodiments, a precursor layer 304 may be disposed between the ILD layer 306 and the etch stop layer 104. In some embodiments, the precursor layer 304 may comprise a TEOS (Tetraethyl orthosilicate) layer.

A metal contact 310, which is separated from the ILD layer 306 by a barrier layer 312, extends vertically through the ILD layer 306 to form an electrical connection between one or more components in the underlying substrate 102 and a top surface 306 a of the ILD layer 306. The metal contact 310 protrudes from the top surface 306 a of ILD layer 306 as a positive relief 314 having a height h above the top surface 306 a of the ILD layer 306. In some embodiments, the “dishing” effect of a CMP process causes a top surface of the positive relief 314 to comprise a concave surface 322.

An additional inter-level dielectric (ILD) layer 320 is disposed above ILD layer 306. A metal wire 316 is comprised within the additional ILD layer 320 at a position that is above the positive relief 314, so that the positive relief 314 of the metal contact 310 is embedded within the metal wire 316. In some embodiments, a barrier layer 308 is located at a bottom surface of the metal wire 316, such that the barrier layer 308 separates the metal wire 316 from the positive relief 314 of the metal contact 310. In some embodiments, an additional barrier layer 318 is also arranged along sidewalls of the metal wire 316 and barrier layer 308.

FIG. 4 is a flow diagram of some embodiments of a method 400 for forming a back-end-of-the-line metal contact.

While the disclosed methods (e.g., methods 200 and 400) are illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act 402, an etch stop layer is deposited onto a substrate. The substrate may comprise any type of semiconductor body (e.g., silicon, SiGe, SOD such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of metal layer, device, semiconductor and/or epitaxial layers, etc., associated therewith.

At act 404, a precursor layer may optionally be deposited above the etch stop layer. In some embodiments, the precursor layer aids in formation of a subsequent dielectric material on a surface of the substrate.

At act 406, an inter-level dielectric (ILD) layer is formed above the substrate. In some embodiments, the ILD layer is formed onto the precursor layer. The ILD layer is formed to a thickness that is equal to the final height of the ILD layer, since it is not subsequently subjected to a chemical mechanical polishing process (e.g., in contrast to ILD 106, which is formed to a greater height that is subsequently subjected to a CMP process).

At act 408, a sacrificial UV/thermal decomposition layer (UTDL) is deposited onto the ILD layer. In various embodiments, the sacrificial UTDL may be deposited by way of chemical vapor deposition (CVD) or spin-coating.

At act 410, an anti-reflective layer (ARL) is formed on the sacrificial UTDL. In various embodiments, the ARL may comprise TEOS (Tetraethyl orthosilicate) oxide, silicon oxynitride (SiON), or nitrogen free and Si, C rich oxide (SiOC/NFARL).

At act 412, a masking layer is selectively formed on the ARL. In some embodiments the masking layer comprises a hard mask.

At act 414, the sacrificial UTDL and the ILD layer are selectively etched according to the masking layer to form one or more via holes. The one or more via holes extend from a surface of the substrate to the etch stop layer.

At act 416, a barrier layer is deposited onto the substrate. The barrier layer is configured to prevent diffusion of metal into the ILD layer. The barrier layer is conformally deposited onto the substrate such that the barrier layer lines the via hole.

At act 418, metal is deposited on the substrate to fill the via hole.

At act 420, a chemical mechanical polishing process, which stops on the sacrificial UTDL, is performed. The CMP process achieves a planarized surface that comprises the sacrificial UTDL, upon which a subsequent metal interconnect layer may be formed.

At act 422, an ultraviolet (UV) exposure or thermal anneal is performed to remove the sacrificial UTDL. Removal of the sacrificial UTDL causes the metal contact to protrude from the ILD layer as a positive relief.

At act 424, a metal wire is formed above the protruding positive relief of the metal contact.

Some embodiments of an exemplary semiconductor substrate, whereon method 400 is implemented, are illustrated in cross-sectional views of FIGS. 5-15.

FIG. 5 illustrates some embodiments of a cross-sectional view 500 corresponding to act 402. Cross-sectional view 500 illustrates an example of a substrate 102. In various embodiments, the substrate 102 may comprise one or more devices and/or one or more underlying metal interconnect layers 302 (e.g., metal wire layers and/or metal contact layers).

An etch stop layer 104 is formed above the substrate 102. In some embodiments, the etch stop layer 104 may comprise a silicon carbide (SiC) layer deposited onto the substrate 102 by way of chemical vapor deposition (CVD).

FIG. 6 illustrates some embodiments of a cross-sectional view 600 corresponding to acts 404-406. As shown in cross-sectional view 600, an inter-level dielectric (ILD) layer 306 is formed above the etch stop layer 104. In various embodiments, the ILD layer 306 may comprise a low-k dielectric material or an ultra low-k (ULK) dielectric material, which have dielectric constants that are small relative to silicon dioxide. For example, the ILD layer 306 may comprise a low-k SiOCH. In some embodiments, the ILD layer 306 may be formed on the substrate 102 using a deposition process or may be grown on the substrate 102 using a thermal oxidation process.

In some embodiments, a precursor layer 304 may be deposited onto the etch stop layer 104 prior to formation of the ILD layer 306. In some embodiments, the precursor layer 304 may comprise a TEOS (Tetraethyl orthosilicate) layer. The precursor layer 304 may be partially or completely consumed during formation of the ILD layer 306.

FIG. 7 illustrates some embodiments of a cross-sectional view 700 corresponding to act 408. As shown in cross-sectional view 700, a sacrificial UTDL 702 is deposited above the ILD layer 306. In some embodiments, the sacrificial UTDL 702 is deposited onto the ILD layer 306 by way of a chemical vapor deposition (CVD). In other embodiments, the sacrificial UTDL 702 may be deposited onto the ILD layer 306 by way of spin coating. In some embodiments, the sacrificial UTDL 702 is deposited to a thickness t having a range of approximately 100 angstrom to approximately 300 angstrom.

The sacrificial UTDL 702 comprises a macromolecular porogen precursor having a formula of CxHyOz, wherein x, y, and z are integers having a value of 0 or greater. In some embodiments, the macromolecular porogen precursor comprises at least one double bond.

FIGS. 8A-8G illustrate some examples of sacrificial UTDL compounds. It will be appreciated that the compounds shown in FIGS. 8A-8G are non-limiting examples of sacrificial UTDL materials.

FIG. 8A illustrates a sacrificial UTDL 800 comprising a porogen of alpha terpinene (ATRP), which has a chemical composition of C₁₀H₁₆.

FIG. 8B illustrates a sacrificial UTDL 802 comprising a porogen of Trimethylcyclohexane (TMC), which has a chemical composition of C₉H₁₈.

FIG. 8C illustrates a sacrificial UTDL 804 comprising a porogen of Cyclohexanone (CHO), which has a chemical composition of C₆H₁₀O.

FIG. 8D illustrates a sacrificial UTDL 806 comprising a porogen of Ethylidene Norborene (ENB), which has a composition of C₉H₁₂.

FIG. 8E illustrates a sacrificial UTDL 808 comprising a porogen of dimethylhexanediamine (DMHD), which has a chemical composition of C₈H₁₄.

FIG. 8F illustrates a sacrificial UTDL 810 comprising a porogen of bicycloheptadiene (BCHD), which has a chemical composition of C₇H₈.

FIG. 8G illustrates a sacrificial UTDL 812 comprising a porogen of cyclohexene oxide (CHOX), which has a chemical composition of C₆H₁₀O.

FIG. 9 illustrates some embodiments of a cross-sectional view 900 corresponding to acts 410-412. As shown in cross-sectional view 900, an anti-reflective layer (ARL) 902 is deposited onto the sacrificial UTDL 702. A masking layer comprising a hard mask 904 is formed above the ARL 902. In some embodiments, the ARL 902 may comprise a nitrogen free ARL (NFARL) deposited by chemical vapor deposition. The nitrogen free ARL comprises an oxide without nitrogen atoms and may contain some carbon atoms (e.g., SiOC). In some embodiments, the hard mask 904 may comprise a titanium nitride (TiN) layer with a deposition process. In other embodiments, the hard mask 904 may comprise other suitable materials such as titanium aluminum nitride (TiAIN), for example.

FIG. 10 illustrates some embodiments of a cross-sectional view 1000 corresponding to act 414. As shown in cross-sectional view 1000, one or more openings that define the location of one or more metal contact layers in the underlying ILD layer 306 are formed in the hard mask 904. An etching process is then performed, in which the substrate is selectively exposed to an etchant 1002 configured to etch one or more underlying layers (e.g., the ARL 902, sacrificial UTDL 702, ILD layer 306, and the precursor layer 304) according to the hard mask 904. The etchant 1002 forms one or more via holes 1004 that extend from a top surface of ILD layer 306 to the etch stop layer 104. In some embodiments, the etching process comprises a dry etching process that uses an etchant 1002 having a F₂/Ar chemistry.

FIG. 11 illustrates some embodiments of a cross-sectional view 1100 corresponding to act 416. As shown in cross-sectional view 1100, a barrier layer 312 is deposited onto the substrate. The barrier layer 312 is deposited to conform to the hard mask 904 and to the sidewalls and bottom of the one or more via holes 1004. In some embodiments, the barrier layer 312 comprises a titanium nitride (TiN) layer deposited by way of deposition process (e.g., a physical vapor deposition such as sputtering) performed in a processing chamber held under vacuum. In other embodiments, the barrier layer 312 may comprise other suitable metals such as tantalum nitride (TaN), tungsten nitride (WN), hafnium nitride (HfN), etc.

FIG. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to act 418. As shown in cross-sectional view 1200, metal 1202 is deposited onto the substrate to fill the one or more via holes 1004. In some embodiments, the metal 1202 may comprise a copper metal deposited by way of physical vapor deposition (e.g., sputtering), for example. In some embodiments, a seed layer may be deposited onto the substrate by way of physical vapor deposition, while the metal 1202 is subsequently formed from the seed layer by way of a plating process (e.g., an electroplating or electroless plating process).

FIG. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to act 420. As shown in cross-sectional view 1300, the surface of the substrate is planarized using a chemical mechanical polishing (CMP) process. The CMP process removes material from the substrate to form a metal contact 310 and to expose the sacrificial UTDL 702 along a substantially flat surface corresponding to line 1302. The CMP process may cause “dishing” in the metal contact 310 that forms a negative relief 1304 so that the metal contact 310 is depressed below a top surface 702 a of the sacrificial UTDL 702 to a depth d. In some embodiments, the “dishing” causes a top surface of the metal contact 310 to comprise a concave surface 322.

FIG. 14 illustrates some embodiments of a cross-sectional view 1400 corresponding to act 422. As shown in cross-sectional view 1400, the sacrificial UTDL 702 is removed by exposing the sacrificial UTDL 702 to a decomposing agent 1402 comprising a UV exposure or a thermal anneal. The decomposing agent removes the sacrificial UTDL 702 from the substrate without additional processing, causing the metal contact 310 and the barrier layer 312 to protrude as a positive relief 314 from an exposed ILD layer 306 by a height, h=t-d. In some examples, the sacrificial UTDL 702 may be exposed to the decomposing agent 1402 (e.g., UV exposure or a thermal anneal) for a time having a range of approximately 1 minute to approximately 15 minutes. In other examples, the sacrificial UTDL 702 may be exposed to the decomposing agent 1402 (e.g., UV exposure or a thermal anneal) for other time periods.

In some embodiments, the UV exposure may expose selective sections of the substrate to UV radiation, while in other embodiments the UV exposure comprises a blanket exposure that exposes the entire substrate to UV radiation. The UV radiation decomposes the sacrificial UTDL 702 to remove the sacrificial UTDL 702 from above ILD layer 306. The UV radiation decomposes the sacrificial UTDL 702 without damaging the metal contact 310 or the underlying ILD layer 306. In some embodiments, the UV exposure is performed in a processing chamber having an environment comprising an ambient gas 1404 comprising a Helium (He) gas, an Ammonia (NH₃) gas, a Nitrogen (N₂) gas, an Argon (Ar) gas, or a Hydrogen (H₂) gas.

In some embodiments, the thermal anneal raises the temperature of the sacrificial UTDL to a temperature in the range of approximately 300° C. to approximately 400° C. In some embodiments, the thermal anneal process may comprise a pre-heating process, which is performed after the CMP process and prior to deposition of an etch stop layer (e.g., for metal wire 316), as part of an etch stop chemical vapor deposition (CVD) process. In such an embodiment, the sacrificial UTDL is removed without introducing new process steps into the back-end-of-the line processing scheme.

FIG. 15 illustrates some embodiments of cross-sectional views 1500 corresponding to act 424. As shown in cross-sectional view 1500, a metal wire 316 is formed on the protruding structure of the positive relief 314. The metal wire 316 is formed within an additional ILD layer 320, located above ILD layer 306, at a position that is above the positive relief 314, such that the positive relief 314 of the metal contact 310 is embedded within the metal wire 316. In some embodiments, a barrier layer 308 is deposited above the metal contact 310 at a bottom surface of the metal wire 316, such that the barrier layer 308 separates the metal wire 316 from the positive relief 314 of the metal contact 310.

It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein, those methodologies are not to be limited by the corresponding structures presented. For example, the methodologies set forth in FIG. 4 are not limited to the structure presented in FIGS. 5-15. Rather, the methodologies and structures are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the FIGs. Additionally, layers described herein can be formed in any suitable manner, such as with spin on, sputtering, growth and/or deposition techniques, etc.

Also, equivalent alterations and/or modifications may occur to one of ordinary skill in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. For example, although the figures provided herein are illustrated and described to have a particular doping type, it will be appreciated that alternative doping types may be utilized as will be appreciated by one of ordinary skill in the art.

In addition, while a particular feature or aspect may have been disclosed with respect to one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein, such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ from that illustrated herein.

Therefore, the present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing.

In some embodiments, the present disclosure relates an integrated chip. The integrated chip comprises a metal contact vertically extending through a first inter-level dielectric (ILD) layer and protruding outward from a top surface of the first ILD layer. A second ILD layer overlies the first ILD layer, and a metal wire is disposed within the second ILD layer. A bottom surface of the metal wire extends from a first height in areas laterally surrounding the metal contact to a second height larger than the first height in areas over the metal contact.

In other embodiments, the present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal stack. The integrated chip comprises a first inter-level dielectric (ILD) layer located over a semiconductor substrate and a metal contact vertically extending through the first ILD layer and protruding outward from a top surface of the first ILD layer as an positive relief. A first barrier layer is disposed on the positive relief of the metal contact. A second ILD layer overlies the first ILD layer, and a metal wire is disposed within the second ILD layer at a position that is vertically separated from the metal contact by the first barrier layer.

In other embodiments, the present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal stack. The integrated chip comprises a metal contact vertically extending through a first inter-level dielectric (ILD) layer and protruding outward from a top surface of the first ILD layer as an positive relief. A second ILD layer overlies the first ILD layer. A metal wire is disposed within the second ILD layer at a position vertically overlying the metal contact, wherein the positive relief of the metal contact is embedded within the metal wire. 

What is claimed is:
 1. An integrated chip, comprising: a metal contact vertically extending through a first inter-level dielectric (ILD) layer and protruding outward from a top surface of the first ILD layer, wherein the metal contact has an upper surface with outer edges arranged over the top surface; a second ILD layer overlying the first ILD layer; and a metal wire disposed within the second ILD layer over the metal contact, wherein a surface of the metal wire facing the metal contact comprises a first recess having sidewalls connecting a lower surface of the metal wire to an interior surface of the first recess over the metal contact.
 2. The integrated chip of claim 1, wherein the metal contact vertically overlaps the metal wire, so that the metal contact is embedded within the metal wire.
 3. The integrated chip of claim 1, wherein a top surface of the metal contact comprises a second recess that extends as a depression from the upper surface to below the upper surface.
 4. The integrated chip of claim 1, further comprising: a first barrier layer vertically disposed between the metal wire and both the metal contact and the first ILD layer.
 5. The integrated chip of claim 4, further comprising: a second barrier layer abutting sidewalls of the metal contact and the first ILD layer and protruding outward from the top surface of the first ILD layer.
 6. The integrated chip of claim 5, wherein the first barrier layer abuts the metal wire, the second barrier layer, and the first ILD layer.
 7. The integrated chip of claim 4, wherein the first barrier layer comprises an inverted ‘U’ shape having a recess facing the metal contact.
 8. An integrated chip having a back-end-of-the-line (BEOL) metal stack, comprising: a first inter-level dielectric (ILD) layer located over a semiconductor substrate; a metal contact vertically extending through the first ILD layer and protruding outward from a top surface of the first ILD layer as a positive relief; a first barrier layer disposed on the positive relief of the metal contact; a second ILD layer overlying the first ILD layer; and a metal wire disposed within the second ILD layer at a position that is vertically separated from the metal contact by the first barrier layer, wherein the metal contact is embedded within the metal wire.
 9. The integrated chip of claim 8, wherein a top surface of the positive relief comprises a concave surface.
 10. The integrated chip of claim 9, wherein the concave surface of the positive relief vertically extends below a second barrier layer abutting sidewalls of the metal contact.
 11. The integrated chip of claim 8, further comprising: a second barrier layer abutting sidewalls of the metal contact and the first ILD layer, wherein the second barrier layer protrudes outward from the top surface of the first ILD layer.
 12. The integrated chip of claim 11, wherein the first barrier layer abuts the metal wire, the second barrier layer, and the first ILD layer.
 13. The integrated chip of claim 8, wherein the first barrier layer comprises an inverted ‘U’ shape having a recess facing the metal contact.
 14. An integrated chip having a back-end-of-the-line (BEOL) metal stack, comprising: a first metal wire layer arranged over a substrate; a metal contact vertically extending from the first metal wire layer, through a first inter-level dielectric (ILD) layer over the substrate, and protruding outward from a top surface of the first ILD layer as a positive relief; a second ILD layer overlying the first ILD layer; a metal wire disposed within the second ILD layer at a position vertically overlying the metal contact, wherein the positive relief of the metal contact is embedded within the metal wire; and a barrier layer arranged between the metal contact and the first ILD layer, wherein the barrier layer protrudes outward from the top surface of the first ILD layer along sidewalls of the positive relief.
 15. The integrated chip of claim 14, wherein a top surface of the positive relief comprises a recess.
 16. The integrated chip of claim 14, further comprising: a first barrier layer vertically disposed between the metal wire and both the metal contact and the first ILD layer, wherein the barrier layer comprises sidewalls that contact the first barrier layer.
 17. The integrated chip of claim 16, wherein the first barrier layer abuts the metal wire and the first ILD layer.
 18. The integrated chip of claim 16, further comprising: a third barrier layer arranged along sidewalls of the metal wire and the first barrier layer.
 19. The integrated chip of claim 16, wherein the first barrier layer contacts the metal wire, the barrier layer, and the first ILD layer.
 20. The integrated chip of claim 14, wherein a top surface of the positive relief comprises a concave surface that vertically extends below upper outer edges of the metal contact. 